The present invention is directed, in general, to substrates for integrated circuit packages and, more specifically, to a system and method for providing mechanical planarization of a sequential build up substrate used in the packaging of a semiconductor device.
Modern semiconductor devices are small in size and may have more than one thousand pins. The most common form of package for such devices is the ball grid array (BGA). The ball grid array package style comprises a substrate made of fiberglass material, an integrated circuit made of silicon, and a protective material to protect the electrical connections between the integrated circuit and the substrate.
FIG. 1 illustrates a sectional side view of an exemplary prior art integrated circuit package 100. Integrated circuit package 100 comprises substrate 120, integrated circuit 130, and protective material 140. Substrate 120 comprises core layer 150, metal layer 160, and dielectric layer 170. As shown in FIG. 1, electrical leads 180 connect integrated circuit 130 with metal layer 160.
xe2x80x9cSequential build upxe2x80x9d is a term used to describe a method of making a multi-layered substrate by sequentially plating layers of metal conductor and layers of dielectric material over a core layer. The sequential build up method is used to make substrates having conductor lines of very small width (e.g., twenty microns (20 xcexcm) to fifty microns (50 xcexcm) in width). Sequential build up substrates are used with integrated circuits that require high density routing.
FIG. 2 illustrates a sectional side view of an exemplary prior art sequential build up (SBU) substrate 200. SBU substrate 200 comprises an underlying core substrate 210. A conventional lamination process is used to place first metal conductor layers 220 and 225 on core substrate 210. First metal conductor layers 220 and 225 form the power or ground planes of substrate 200. First dielectric layers 230 and 235 are applied by screening or roller on the first metal conductor layers 220 and 225. Circuit elements 240 and 245 (e.g., conductor lines 240 and 245) are then placed on first dielectric layers 230 and 235 using a prior art metal plate, pattern and etch process. The circuit elements 240 and 245 are then covered with second dielectric layers 250 and 255. These layers are usually done in pairs as top and bottom layers for efficiency. However, the layers can also be built one side at a time.
As shown in FIG. 2, the external surface of second dielectric layers 250 and 255 that cover circuit elements 240 and 245 are not flat. Consequently, the external surfaces of third metal conductor layers 260 and 265 that are placed over second dielectric layers 250 and 255 are also not flat. This makes it difficult to make precise images on the external surface of third metal conductor layers 260 and 265. As a result of the presence of uneven surfaces of second dielectric layers 250 and 255 and of third metal conductor layers 260 and 265, substrates that are created by the xe2x80x9csequential build upxe2x80x9d method are limited to two or three metal buildup layers.
It would be desirable to have a system and method for creating flat surfaces in xe2x80x9csequential build upxe2x80x9d layers. For example, if second dielectric layers 250 and 255 and third metal conductor layers 260 and 265 had flat surfaces, then it would not be difficult to make precise images on the flat external surfaces of third metal conductor layers 260 and 265. If xe2x80x9csequential build upxe2x80x9d layers could be constructed with flat surfaces, then the xe2x80x9csequential build upxe2x80x9d method would not be limited to two or three metal buildup layers.
There is a need in the art for an improved system and method for providing mechanical planarization of a sequential build up substrate for an integrated circuit package.
There is a need in the art for an improved system and method for increasing the number of sequential buildup layers that may be placed on a substrate for an integrated circuit package.
To address the deficiencies of the prior art, it is a primary object of the present invention to provide a system and method for providing mechanical planarization of a sequential build up substrate for an integrated circuit package.
The present invention comprises an improved system and method for manufacturing a substrate for an integrated circuit package. Circuit elements are placed on a first dielectric layer of a substrate using a prior art metal plate, pattern and etch process. Then filler circuit elements are placed between functional circuit elements on the first dielectric layer of the substrate. A second dielectric layer is then placed over the functional circuit elements and the filler circuit elements and the first dielectric layer. A planarization plate with a heating element is then placed in contact with the uneven external surface of the second dielectric layer before it is cured. The planarization plate with a heating element is pressed onto the uneven portions of the external surface of the second dielectric layer to create a flat external surface on the second dielectric layer. Then, continued heating causes the dielectric layer to cure and harden. After the flat external surface of the second dielectric layer has cooled, it is then covered with a metal conductor layer. Because the external surface of the second dielectric layer is flat, the external surface of the metal conductor layer that covers it will also be flat. The improved flatness of the second dielectric layer and consequently the improved flatness of the associated metal conductor layer permits more layers to be added before a critical cumulative surface roughness is reached which prevents the accurate photoimaging that is required to produce high quality sequential build up substrates.
It is an object of the present invention to provide an improved system and method for providing mechanical planarization of a sequential build up substrate for an integrated circuit package.
It is also an object of the present invention to provide an improved system and method for increasing the number of sequential build up layers that may be placed on a substrate for an integrated circuit package.
It is another object of the present invention to provide an improved system and method for creating dielectric layers in a substrate that have a flat external surface.
It is another object of the present invention to provide an improved system and method for heating an uneven surface of a dielectric layer during the manufacture of a substrate to flatten portions of the uneven surface of the dielectric layer in order to create a flat external surface on the dielectric layer.
It is yet another object of the present invention to provide an improved system and method for controlling the thickness of a dielectric layer during the manufacture of a substrate when a flat external surface on the dielectric layer is created.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words or phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9corxe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior uses, as well as to future uses of such defined words and phrases.